The present invention relates to semiconductor device manufacturing, and more particularly to a flash memory device and method of making a semiconductor device.
Information storage devices, i.e., memories, are widely used in data processing systems. Semiconductor memory devices can be largely divided into two groups: volatile memory devices and non-volatile memory devices. The volatile memory device loses data stored in memory cells when power is removed. The non-volatile memory device, however, preserves data stored in memory cells when power is removed from the memory. Among non-volatile memory devices, NAND type flash memory with a serial memory cell structure is becoming important in the art due to its high degree of integration density.
The flash memory device has a programming mode, an erasing mode and a reading mode. The device requires a common source line to provide a ground voltage during the reading mode. In a conventional method of forming a common source line in a flash memory device, a gate oxide layer, a floating gate polysilicon layer, an inter-gate insulating layer and a control gate polysilicon layer are sequentially formed on a semiconductor substrate. Through photolithographic processes, the stacked layers are patterned to form a stacked gate pattern. Impurities are implanted into the substrate using the stacked gate pattern as an implanting mask to form source/drain regions outside of the stacked gate pattern. An interlayer insulating layer is deposited on the resulting structure. Using a photoetching process, the interlayer insulating layer is patterned to form a contact hole, exposing a predetermined source/drain region of the semiconductor substrate. A conductive layer is then deposited in the contact hole and on the interlayer insulating layer. A planarization process such as an etch-back or a chemical mechanical polishing (CMP) is carried out to leave the conductive layer in the contact hole and remove the portion of the conductive layer that is outside of the contact hole, thereby forming a common source line. An insulator is deposited on the resulting structure having the common source line. Using photolithographic processes, the insulator and the interlayer insulating layer are sequentially patterned to form a bit line contact hole. A conductive material is formed in the bit line contact hole and on the insulator and is patterned to form a bit line.
This conventional method has certain drawbacks. Since the conventional method requires photolithographic processes to form a contact hole for a common source line, misalignment can occur. This can cause undesirable etching of the stacked gate pattern and a resulting electrical bridge between the stacked gate pattern and the common source line. Also, since the common source line is formed after the formation of the stacked gate pattern, problems with the bit line process can arise. During the formation of the bit line contact hole, both the interlayer insulating layer that insulates the stacked gate pattern and the common source line and the insulator that insulates the common source line the bit line are etched. These layers to be etched are so thick that the bit line contact hole can be opened imperfectly. If the thicknesses of the insulators are reduced in order to avoid this imperfect opening of the bit line contact hole, the common source line can be exposed during patterning of the bit line, thereby causing a short between the bit line and the common source line.
The present invention is directed to an approach to forming a flash memory device which solves these drawbacks found in the prior art. In particular, the invention is directed to formation of a flash memory device in which short circuits between a bit line and a common source line are avoided.
A feature of the present invention is that the common source line is made of the same layer as a floating gate of a stacked gate pattern. The common source line is patterned together with the stacked gate pattern in the same photolithographic process. Also, during this photolithographic process, a butted contact can be defined. The resulting common source line is lower in level than the stacked gate pattern. As a result, processes for forming the common source line can be simplified. Also, the thickness of the layers to be etched during bit line contact process can be reduced without reducing the distance between the bit line and the common source line, thereby providing a reliable bit line contact process.
In accordance with the present invention, there is provided a method of forming a flash memory device. In accordance with the method, a material layer is formed on a semiconductor substrate where a stacked gate pattern forming region and a common source line forming region are defined. The material layer is patterned to form an opening exposing the common source line forming region. A floating gate conductive layer, an inter-gate insulating layer and a control gate conductive layer are formed on the material layer and in the opening. The control gate conductive layer, the inter-gate insulating layer, the floating gate conductive layer and the material layer are patterned to form a stacked gate pattern on the stacked gate pattern forming region and to form a common source line in contact with the common source line forming region through the opening.
In one embodiment, a mask insulating layer, having an etching selectivity with respect to the inter-gate insulating layer, is formed on the control gate conductive layer. Patterning the control gate conductive layer, the inter-gate insulating layer, the floating gate conductive layer and the material layer includes patterning the mask insulating layer and the control gate conductive layer until the inter-gate insulating layer is exposed to form a control gate pattern aligned over the stacked gate pattern forming region. A photoresist layer pattern is formed on the inter-gate insulating layer, the photoresist layer pattern being in parallel with the control gate pattern and running over the common source line forming region. Using the photoresist layer pattern and the mask insulating layer of the control gate pattern, the inter-gate insulating layer, the floating gate conductive layer and the material layer are sequentially patterned.
In one embodiment, the floating gate conductive layer is formed of a polysilicon layer. The control gate conductive layer can be made of a stacked layer of polysilicon and tungsten silicide. The inter-gate insulating layer can be formed of an ONO (oxide-nitride-oxide) layer. The mask oxide layer can be formed of an oxide layer by a plasma enhance chemical vapor deposition technique. The material layer can be made of a gate oxide layer or a combination gate oxide/polysilicon layer.
After the opening is formed, impurities of the conductivity type opposite to the conductivity type of the semiconductor substrate are implanted to the semiconductor substrate. This provides a conductive path to the common source line forming region.
In one embodiment, after the stacked gate pattern and the common source line are formed, an insulator is formed. A bit line can be formed on the insulator to intersect the common source line.
In accordance with the present invention, there is provided a flash memory device cell. The flash memory device cell includes a plurality of stacked gate patterns formed on a semiconductor substrate. Each stacked gate pattern is made of a gate insulator pattern, a floating gate pattern over the gate insulator pattern, an inter-gate insulator pattern over the floating gate pattern and a control gate pattern over the inter-gate insulator pattern. The stacked gate pattern also includes a common source line made of the same layer as the floating gate pattern.
In one embodiment, the floating gate pattern is made of a first floating gate and a second floating gate, and the common source line is made of the second floating gate. The floating gate pattern can be made of polysilicon, the control gate pattern can be made of a stacked layer of polysilicon and tungsten silicide, and the inter-gate insulator pattern can be made of an ONO (oxide-nitride-oxide) layer.
In one embodiment, the flash memory device cell further includes a plurality of trench isolation regions formed at predetermined portions of the semiconductor substrate and defining a plurality of active regions therebetween. A plurality of common source line regions can be formed between predetermined stacked gate patterns. In this configuration, the plurality of stacked gate patterns intersect the plurality of trench isolation regions and the active regions. The common source line can be in parallel with the stacked gate patterns and can be in contact with the common source line regions and the plurality of trench isolation regions.
In one embodiment, the memory device cell also includes an insulation layer covering the plurality of stacked gate patterns and the common source line. A bit line is formed on the insulating layer, the bit line intersecting the common source line. In accordance with the present invention, there is provided a method of forming a flash memory device. The method includes forming a plurality of trench isolation regions defining active regions on predetermined portions of a semiconductor substrate of a first conductivity type, and forming a gate oxide pattern and a first floating gate pattern on the active regions. The first floating gate pattern and the gate oxide pattern are sequentially patterned to form openings exposing predetermined portions of the active regions. Impurities of a second conductivity type are implanted into the exposed active regions by the openings to form common source line regions. A second floating gate pattern is formed to cover the first floating gate pattern and the common source line regions and expose the trench isolation regions. An inter-gate insulating layer is formed on the resulting structure. A plurality of control gate patterns are formed on the inter-gate insulating layer to intersect the active regions and the trench isolation regions. A photoresist layer pattern is formed on the inter-gate insulating layer between the control gate patterns, the photoresist layer pattern being in parallel with the control gate patterns and running over the common source line regions. Using the photoresist layer pattern and the control gate patterns, the inter-gate insulating layer, the second floating gate pattern and the first floating gate pattern are sequentially patterned to form a plurality of stacked gate patterns and a common source line, the stacked gate patterns intersecting the active regions and the trench isolation regions, and the common source line being in contact with the common source line regions and in contact with portions of the trench isolation regions and in parallel with the stacked gate patterns.
In one embodiment, the control gate pattern is made of a control gate conductive layer pattern and a mask insulator pattern. The mask insulator pattern has an etching selectivity with respect to the inter-gate insulating layer. The first and second floating gate patterns can be made of polysilicon. The control gate conductive layer pattern can be made of a combination polysilicon/tungsten silicide. The inter-gate insulating layer can be made of an ONO(oxide-nitride-oxide) layer. The mask insulator pattern can be made of an oxide by a plasma enhanced chemical vapor deposition technique.
Sequentially patterning the first floating gate pattern and the gate oxide layer to form openings exposing predetermined portions of the active regions can also expose a predetermined region of the trench isolation where a scribe line is to be made. Also, the photoresist layer pattern can be further formed on the inter-gate insulating layer to cover a butted contact forming region. Herein, a butted contact is formed while sequentially patterning the inter-gate insulating layer, the second floating gate pattern and the first floating gate pattern.
In one embodiment, forming a plurality of trench isolation regions, a gate oxide pattern and a first floating gate pattern on the semiconductor substrate includes sequentially forming a gate oxide layer, a first floating gate layer and a nitride layer on the semiconductor substrate. The nitride layer, the first floating gate layer and the gate oxide layer are sequentially patterned to form a trench etching mask. Using the trench etching mask, the semiconductor substrate is etched to form a plurality of trenches. The trenches are filled with an insulating material, and the nitride layer is removed.